1. Field of the Invention
This invention pertains to the field of microelectronic chip fabrication for logic, memory, communication and microcontroller applications.
2. Description of the Prior Art
The operating speeds of silicon integrated circuits are increasing at phenomenal rates to meet aggressive performance demands in computing, communication and microcontroller applications. This in turn necessitates that the signal propagation delays in the wiring that is used to interconnect the circuits on a chip be reduced so that the performance is not limited or hampered unduly by interconnect delays. Interconnect delays in chips are due to the RC time constants wherein R is the resistance of the on chip wiring and C is the effective capacitance between the signal lines and the surrounding conductors in the multilayer interconnection stack. The resistance of the wiring can be reduced by using a material with a lower specific resistivity than the currently used Al-rich Alxe2x80x94Cu alloys. Copper, which has half the specific resistivity of Alxe2x80x94Cu alloys, is the prime candidate being explored for this purpose. The capacitance of a signal line is a combination of the mutual capacitance between the lines in the same wiring plane (CLL) and between lines in two different levels (CCO or CLG) as shown in FIG. 1, cited from a recent conference (R. Havemann presented at the Proceedings of the 1996 Symposium on VLSI Technology, Honolulu, Hi., Jun. 10, 1996). As shown in the graph associated with this schematic, when feature sizes decrease, the intralevel capacitance CLL becomes the major part of the interconnect capacitance and hence dominates the interconnect delay. Interconnect capacitance can be reduced by reducing the dielectric constant, K, of the insulating medium that surrounds these lines. Hence, there has been a significant effort to identify and use low K insulators in interconnect structures. A whole gamut of insulator materials including fluorinated silica, polymers with and without fluorination, amorphous teflon-like polymers, and aerogels made of porous silica have been proposed as possible low K materials for this purpose.
Progress is being made in fabricating interconnect wiring with copper as the conductor. Since copper, unlike Al, is difficult to pattern by subtractive plasma etching, a xe2x80x9cDamascenexe2x80x9d process is favored to fabricate copper features embedded in a dielectric medium. One typical version of this process, known as the xe2x80x9cdual damascenexe2x80x9d process, is described briefly below as an example. After the devices are fully fabricated on a semiconductor wafer, the surface is coated with an ionic barrier such as phosphosilicate glass (PSG), borophosphosilicate glass (BPSG) or silicon nitride and appropriate vias are defined in this barrier by photolithography and etching at locations where contacts for interconnect wiring are required. Subsequently, the etched features are filled with an appropriate conductor such as tungsten.
For the sake of clarity and simplicity, we depict the wafer at this stage of processing as the semiconductor substrate, 10, in FIGS. 2A to 2D and later in FIGS. 4A to 4D. Two layers of dielectrics, 20 and 30, are applied on the semiconductor substrate and patterned by lithography and plasma etching to produce trenches, 50, on the top layer that represent the wiring tracks and vias, 40, in the lower layer that will become the means to connect the wires to the metal level below, as shown in FIG. 2A. Layers 20 and 30 can be made of the same dielectric in which case they can be applied in a single deposition step. In a next step, an electrically conductive barrier/adhesion layer, 60, and a copper-based conductor layer, 70, are deposited on the patterned dielectric structure by one or more of the techniques such as sputtering and/or chemical vapor deposition and electrolytic or electroless plating. This layer has to be thick enough to overfill the vias, 40, and trenches, 50, as shown in FIG. 2B.
The last step is to planarize the top surface by chemical-mechanical polishing (CMP) so that the excess copper and the barrier layer are polished off from the top surface resulting in the inlaid wire/via stack as shown in FIG. 2C. This sequence is repeated several times till the necessary number of wiring layers are built. In a final step, the wafer is coated with an insulating passivation layer, 80, and terminal metal pads, 90, are deposited and connected to the top most wiring level through suitable vias in the passivation layer, 80, as shown in FIG. 2D. These terminal pads are used to assemble the chip on a chip carrier using solder interconnects which enables the chip to communicate with other chips and to send and receive information to the user. Alternate terminal pad processes and structures can also be used in place of the final step described above which enable interconnection using wire bonding, conductive paste bonding and the like. Usually, the wafers are subjected to a 400xc2x0 C. anneal in a N2/H2 mixture to xe2x80x9canneal outxe2x80x9d any damage accumulated in the thin gate oxide under the silicon circuit gates due to the various plasma processes used to fabricate the wiring structure.
There are several practical difficulties in integrating the low K dielectric materials in such a wiring structure. First, the physico-chemical properties of many of these low K materials are not optimum for the CMP process. For example, most of the polymer materials are too soft and get eroded at too fast a rate relative to copper during CMP, to allow good control over the inlaid layer thickness. Fluorinated oxide dielectrics are suspected to react with or be prone to reaction with wiring metallurgies leading to corrosion and adhesion loss. Some of these issues can be contained by applying a hard mask layer over the dielectric to act as a CMP stop layer but this requires additional processing and one has to ensure compatibility of the low K material with the processing of this additional layer. Second, most of the low K polymers degrade under thermal excursions to temperature at or above 400xc2x0 C. Hence, they are not suitable for the device interconnection application because they cannot withstand the device damage anneal alluded to above. This severely restricts the choice of dielectric, which can be used for this purpose. Last, the porous inorganic dielectrics such as aerogels are mechanically weak and friable and are unlikely to withstand the multilayer build process of repeated metal deposition and CMP described above.
Another concern is the penetration of copper into the dielectric materials during the various thermal excursions encountered or the fabrication of the interconnect stack and the final damage anneal step. This can degrade the insulator""s dielectric constant and leakage performance and, in some cases, facilitate the migration of copper to the device levels during the service life of the chips, leading to device failure. Accordingly, the adhesion/barrier layer described above has to function as a copper diffusion barrier. To achieve this reliably, the adhesion/barrier layer has to be free of defects and rapid diffusion paths such as grain boundaries. This in turn requires conductive barrier films of sizable film thickness. Since the typical conductive barrier films have high electrical resistivity, the presence of a significant thickness of such a film in the conductor cross section leads to an increase in the effective line resistance of the wiring. This is particularly severe for narrow lines typical of advanced chips, where the barrier thickness becomes a significant fraction of the line width itself.
Many of the low K dielectrics are also not compatible with Alxe2x80x94Cu interconnect processing because 400xc2x0 C. to 450xc2x0 C. substrate temperatures during deposition and/or post deposition anneals are still required to achieve reliable microstructure and properties of the Alxe2x80x94Cu lines, and repeated excursions to such temperatures (in addition to the final device damage anneal) tend to lead to degradation of many of the low K polymeric insulators, as mentioned earlier.
There are two methods of prior art that claim to address the issues alluded to above.
The first one is a method reported by Jeng et al., (Proceedings of the 1995 International Symposium on VLSI Technology, Systems and Applications, pp. 164-168). Their method is cited pictorially in FIG. 3 from the above referenced publication. These authors propose to fabricate an Al-based wiring level by deposition and subtractive etching; CVD deposition of a low K polymer dielectric (such as Parylene) which conformally coats widely spaced features and fills and planarizes over very narrow spaces between closely spaced lines; plasma or RIE etching of the polymer such that it is nearly removed from the wide spaces while being left intact between the narrow spaces; applying a silicon oxide dielectric overcoat and planarizing the structure; etching the via holes in the oxide layer, depositing metal fill and planarizing; and repeating the sequence to construct the required multilevel interconnect structure.
This method suffers from several limitations. First, the level of conformality versus planarity of the CVD polymer coating is dependent on the feature size and spacing and hence will be pattern dependent within the same wafer. This makes it difficult to ensure definitively what the exact nature of the dielectric medium would be around any given line in an interconnect design. This makes the task of predicting and accounting for interconnect delays in chip designs very difficult. Second, the process is tailored to work with the subtractively patterned Al-based wiring structures and may not be suitable for the dual damascene process (Al or Cu based) since the dielectric layers with trenches or vias are made first and metal is filled in and planarized with the patterned dielectric stack in a subsequent step. This precludes the use of the processing route described in FIG. 3, proposed by Jeng et al., for interconnect structures fabricated by the damascene process.
The second method taught by Chang et al., U.S. Pat. No. 5,559,055, describes a process in which one layer of aluminum-based interconnect wiring, the insulator (silicon dioxide) and a stud layer deposited into the vias in the insulator are first fabricated. A second interconnect wiring layer of Al alloy is then deposited and patterned on top. At this point, the insulator is removed either completely or only from between the metal features by an etching process. The structure is then either fully or partially filled with a lower dielectric constant material. A passivation layer is then deposited over the resulting structure. A net lowering of the dielectric constant is claimed due to the replacement of the oxide material with a lower K insulator with or without trapped voids filled with air.
While this method, in principle, can achieve a uniform and lower effective K value in the structure when the etched gaps are completely filled with a low K dielectric, their structure with partially voided low K dielectric will not yield a uniform or predictable value of effective K. This is due to the fact that the presence or absence of voiding depends in a complex manner on a myriad of factors including the size, spacing and aspect ratio of the metal features and, for solution-based insulator deposition, the viscosity and the solvent content of the filling insulator precursor solution. In an actual microelectronic chip where these feature attributes can vary over a large range in any given metal level this would lead to uncontrolled and unpredictable combination of voided and filled areas making it very difficult to assign an effective dielectric constant. This further complicates the job of designing circuits since the design rules require that the effective dielectric constants be precisely known and be maintained within a narrow range to achieve minimized delay tolerances and hence improved chip performance. Further, Chang et al. teach a method that is restricted to wiring structures based on subtractively etched metal lines (aluminum based) only and do not teach a method to achieve lower effective K in structures made by a damascene process, as described in FIG. 2.
It is an object of the present invention to provide a method to achieve a low K chip interconnect structure made of copper based or Al based alloys by circumventing the problems and limitations described above.
It is another object of the present invention to produce a chip interconnection structure that comprises copper or aluminum alloy based interconnect wiring disposed in a low K dielectric (preferably air) predominantly situated as the intralevel dielectric so as to reduce the intralevel capacitance which is the major portion of the interconnect capacitance in closely spaced interconnection wiring.
It is yet another object of the present invention to fabricate these interconnect structures with the readily available set of semiconductor processing tools and materials.
A broad aspect of the present invention is a low dielectric constant chip interconnect wiring structure.
The present invention includes a microelectronic interconnect wiring structure comprising a plurality of wiring and via levels, each said level containing a plurality of metal features, an interlevel dielectric vertically separating said metal features located in different ones of said levels, said interlevel dielectric being predominantly a solid, thermally stable and easily processable dielectric, and an intralevel dielectric laterally separating any of said metal features contained in the same level from one another, said intralevel dielectric being predominantly air, thereby resulting in a lower overall interconnect capacitance.
The present invention further includes a microelectronic interconnect wiring structure comprising a plurality of wiring and via levels, each said level containing a plurality of metal features, an interlevel dielectric vertically separating said metal features located in different ones of said wiring levels, said interlevel dielectric being predominantly a solid, thermally stable and easily processable dielectric material, a first intralevel dielectric laterally separating metal features in a first set of wiring levels, said first intralevel dielectric being predominantly a solid, thermally stable, low k dielectric material with a dielectric constant range of 1 to 4, a second intralevel dielectric laterally separating metal features in a second set of wiring levels and said second intralevel dielectric being predominantly air, thereby resulting in a lower overall interconnect capacitance.
The present invention still further includes a multilevel air-gap-containing interconnect wiring structure comprising: a collection of interspersed line levels and via levels, said via levels and line levels containing conductive via and line features embedded in a dielectric comprising an air-gap and solid dielectric, said air-gap and solid dielectric comprising: (i) one or more solid dielectrics only in the shadows of said conductive features in overlying levels; and (ii) a gaseous dielectric elsewhere in said structure; wherein said collection of line levels and via levels are topped by a laminated thin, taut insulating cover layer having openings to selected conductive features in the topmost underlying line or via layer, and wherein said openings are filled with conductive material connecting to terminal pad contacts on said insulating cover layer.